The present invention relates to testing of an integrated circuit die or flip-chip, and more particularly to testing the integrated circuit die using a probe card.
In the last few decades, the electronics industry has literally transformed the world. Electronic products are used by, or affect the daily lives of, a large segment of the world's population. For example, telephones, television, radios, Personal Computers (PCs), laptop PCs, palmtop PCs, PCs with built-in portable phones, cellular phones, wireless phones, pagers, modems, and video camcorders, are just a few of the electronic products that have been developed in recent years and which have been made smaller and more compact, while providing more and/or enhanced functions than ever before. The integrated circuit (IC) die or IC chip, and the more efficient packaging of the IC die, have played a key role in the success of these products.
There are three distinct stages in the manufacture of an IC die. The first stage is the material preparation. In this stage, the raw materials are mined and purified to meet semiconductor standards. The second stage consists of forming the material into wafers. The diameters of the wafers can vary between 1 and 12 inches. In the third stage, wafer fabrication, the IC dies are formed in and on the wafer. Up to several thousand can be formed on a wafer but 200 to 300 are more common.
There are several different types of packaging configurations that may be used with IC dies. Some types require wire bonding of the IC die to traces on a package substrate. Wire bonding presents several problems such as minimum height limits that are imposed by the required wire loops and a chance of electrical performance problems or shorting if the wires come too close to each other. The wire bonds require two bonds, one at each end of the wire, and must be placed one-by-one. Moreover, there are resistances associated with each bond.
One way to avoid the above problems associated with wire bonding is to eliminate the wires and use a "flip-chip". The term flip-chip derives its name from the way the IC die or chip is attached to a package substrate. Deposited metal "bumps" are formed on each bonding pad on the upper surface of the IC die. To attach the IC die to the package substrate, the IC die is "flipped" over and the "bumps" are soldered to corresponding inner leads or traces on the package substrate. Advantageously, flip-chip packages are lower profile, the electrical connections have lower resistance, and the electrical path is much shorter. One well known device manufacturer, IBM, refers to its version of this technology as "controlled collapse chip connection (C4)".
Formation of the IC dies on the wafer--the wafer fabrication process--requires a high degree of precision in process control, equipment operation, and material manufacture. One mistake can render the wafer completely useless. Throughout the process, various tests and measurements are made to determine both the wafer and process quality. Increased wafer volumes and more critical processes require more in-line testing.
After wafer fabrication is completed, the IC dies on the wafer must be electrically tested. The basic equipment required to perform electrical tests are a probe machine with the capability of positioning needle-like probes on the IC die contact pads or "bumps"; a switch box to apply a test signal, e.g., a voltage or current of a selected polarity to the "bumps"; and a method of displaying the results. In advanced systems, the probe station may be automated to sequentially test several IC dies. Typically, the IC die measurements are made by applying a voltage to the component contact probe and measuring the resultant current flowing between the "bumps". The results of such measurements are then displayed on a display screen.
The increasing complexity and circuit density of integrated circuits on semiconductor substrates requires increasingly more dense electrical connections to be made over the surface area of such substrate. Current fabrication methods allow IC dies to have over 1000 contact pads or "bumps" formed on the surface of the IC die. These bumps are physically and electrically tested at one time or another during fabrication or wafer sort. In current practice, test probes are assembled and arranged in a pattern corresponding to the physical layout of the bump area array on the surface of the IC die. The probes are then wired to a tester, usually using manually soldered jumper wires between the contact probes and conductors of the test channels of the test equipment. Disadvantageously, such probe fabrication is tedious, expensive and subject to human error. Manual soldering and the use of wire jumpers also limits the number of bumps on an IC die that can be tested because there is a minimum area between the probes and wires needed for the connections, thus limiting the number of bumps that can be tested.
One method that has been used to eliminate the wire jumpers is to insert a transition unit or "interposer" between the probe assembly and the test channels. The interposer transposes the physical array of the spatially ordered probes that are mounted to connect with bumps on the IC die into another physical array of contacts that connect with conductors of the test channels. Unfortunately, using an interposer adds another level of complexity and cost to the testing of the wafer and IC dies.
In view of the above, it is evident that what is needed is a apparatus and method of testing an integrated circuit die or flip-chip with a high number of bumps that provides contact with all the bumps, can be used with many size wafers or components, can be used on the wafer without damaging it, and eliminates the wire jumpers, thereby reducing the level of complexity of the testing process and making the testing more cost effective.